Electrical circuits consist of a variety of components, for example, resistors, capacitors, inductors, diodes and transistors. When designing an electrical circuit, the circuit is expected to satisfy certain user-specified requirements. The creation of a complex circuit typically involves creation of a topology, component sizing and placement, and also routing of wires that interconnect the circuit's components.
By ‘placement’ is meant assignment of each of the circuit's components to a particular physical location on, e.g., a printed circuit board or a silicon wafer. By ‘routing’ is meant assignment of a particular physical location to wires interconnecting the leads of the circuit's components.
The physical location of the components and wires may affect the overall behavior of the circuit to some extent because electrical components and wires may have interactions with one another based on their physical dimensions and location. These interactions, generally called parasitic effects, are generally small and may not be important to the performance of relatively ‘simple’ circuits operating at relatively low frequencies. In such cases, parasitic effects may simply be factored out. By ‘parasitic effect’ is meant undesired effect caused by capacitance, resistance, and sometimes inductance, which are introduced by wires that interconnect devices in a circuit.
Parasitic effects may detrimentally affect the performance of a more complex circuit or a circuit operating at relatively high frequencies, for example, at radio frequencies (“RF”) or higher frequencies. Under such circumstances, it may be impossible to design a practical circuit without factoring in parasitic effects.
Electric wires are known for introducing an overall intrinsic parasitic capacitance that is a function of a capacitance-per-unit length value (e.g., 15 pF/meter). Therefore, the longer the wire, the greater is its intrinsic parasitic capacitance, and the more detrimental effect it would likely to have on the performance of the full custom circuit involved.
For the reasons described hereinbefore, delay models (or, equivalently, wire model objects) that are useful for timing analysis simulations, are required in order to evaluate the temporal functionality of the designed circuit at high operating frequencies. A ‘wire model object’ (“WMO”) typically consists of resistor and capacitor elements arranged in a way to reflect as closely as possible parasitic effects associated with a specific wire, or a signal path. A WMO is inserted into (i.e., to replace wires in) the circuit in the schematic sense, between corresponding circuit elements or devices and instead of the wire it replaces.
WMOs are widely used in the design process of circuits, as they are a major tool for evaluating time performance of the circuits before they are actually laid out and fabricated. More specifically, after setting the placement of the circuit elements and wiring routing, WMOs are schematically inserted into several locations in the circuit schematics to replace wire segments, or sections, that are suspected as problematic (in terms of time performance). Then, time simulations are typically performed on the circuit schematics to evaluate parasitic effects that might be induced by real wires; that is, assuming the wires are routed according to the estimated wiring routing. The results of the time analysis will determine whether components will have to be resized and re-placed. If the time analysis is favorable, the circuit may be fully laid out and prepared for fabrication. Otherwise, the problematic circuit portions may have to be reformulated.
The type (i.e., the individual elements and their arrangement) of a WMO is generally determined by several parameters, such as, but not limited to, the length, width type of metal of the planned wire.
However, wire model objects are traditionally calculated and inserted into circuit schematics manually, which is troublesome, as explained hereinafter. Therefore, wire models can be used only in respect of a relatively small number of wires, which is problematic because even relatively simple circuits include large number of interconnection, and other type of wires. For this reason, in the traditional wires modeling, a circuit designer has first to intuitively identify wires as ‘critical wires’ and, then construct, or calculate, wire models only in respect of the ‘critical wires’. Therefore, using wire model objects in the traditional manner is far from being satisfactory for circuits consisting of thousands, and even hundreds, of devices (e.g., logical gates). Put simply, it is impractical to manually construct delay models for a large number of wires. By intuitively determining critical wires, a circuit designer may erroneously think of non-critical wires as critical ones. On the other hand, the circuit designer may inadvertently overlook ‘real’ critical wires. For the reasons described hereinbefore, when a circuit's schematic is designed, only an incomplete ‘picture’ of the overall potential parasitic effects is factored in when performing the timing analysis.
Therefore, a need exists for automated modeling procedure in respect of interconnection, and other types of, wires.
Another need exists to provide a method for fast, reliable and convenient modeling of interconnection, and other types of, wires in a circuit's schematic.
A further need exists to provide a method for allowing modeling some or all the wires associated with a circuit's schematic design.